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MOSEL VITELIC
V53C808H HIGH PERFORMANCE 1M x 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH
35
35 ns 18 ns 14 ns 70 ns
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 15 ns 75 ns
45
45 ns 22 ns 17 ns 80 ns
50
50 ns 24 ns 19 ns 90 ns
Features
s 1M x 8-bit organization s EDO Page Mode for a sustained data rate of 72 MHz s RAS access time: 35, 40, 45, 50 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Optional Self Refresh (V53C808SH) s Refresh Interval: 1024 cycles/16 ms s Available in 28-pin 400 mil SOJ package s Single +5V 10% Power Supply s TTL Interface
Description
The V53C808H is a ultra high speed 1,048,576 x 8 bit CMOS dynamic random access memory. The V53C808H offers a combination of features: Page Mode with Extended Data Output for high data bandwidth, and Low CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Page Mode with Extended Data Output operation allows random access of up to 1024 x 8 bits within a row with cycle times as fast as 14 ns. The V53C808H is ideally suited for graphics, digital signal processing and high-performance computing systems.
Device Usage Chart
Operating Temperature Range 0C to 70 C Package Outline K * T * 35 * Access Time (ns) 40 * 45 * 50 * Power Std. * Temperature Mark Blank
V53C808H Rev. 1.5 April 1998
1
MOSEL VITELIC
Part Name
V53C808HKxx V53C808HTxx V53C808SHKxx V53C808SHTxx
V53C808H
Supply Voltage
5V 5V 5V 5V
Self Refresh
No Self Refresh No Self Refresh Optional Standard Self Refresh (16ms) Optional Standard Self Refresh (16ms)
Package
SOJ TSOP SOJ TSOP
Speed
35/40/45/50 35/40/45/50 35/40/45/50 35/40/45/50
V
5
3
C
8
0
8
S
H
FAMILY
DEVICE SUPPLY VOLTAGE
PKG
S (OPTIONAL STANDARD SELF REFRESH)
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL) 35 40 45 50 (35 ns) (40 ns) (45 ns) (50 ns)
H (5V) K (SOJ)
808H-01
28-Pin Plastic SOJ PIN CONFIGURATION Top View
VCC I/O1 I/O2 I/O3 I/O4 WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
808H-02
Pin Names
A0-A9 RAS Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A9 A8 A7 A6 A5 A4 VSS
CAS WE OE I/O1-I/O8 VCC VSS NC
400 mil
V53C808H Rev. 1.5 April 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature Under Bias ................................. -10C to +80C Storage Temperature (plastic) ..... -55C to +125C Voltage Relative to VSS .................-1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.4 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C808H
TA = 25C, VCC = 5 V 10%, f = 1 MHz
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
Capacitance*
* Note: Capacitance is sampled and not 100% tested
Block Diagram
1M x 8
OE WE
CAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0 -Y 9
I/O 1 I/O 2 I/O 3
SENSE AMPLIFIERS
1024 x 8
I/O BUFFER
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8
REFRESH COUNTER
10 A0 A1
ADDRESS BUFFERS AND PREDECODERS
X0 -X9
ROW DECODERS
1024
* * *
A7 A9
MEMORY ARRAY 1024 x 1024 x8
808H-04
V53C808H Rev. 1.5 April 1998
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MOSEL VITELIC
DC and Operating Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified. Access Time V53C808H Min.
-10
V53C808H
Symbol
ILI ILO ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Typ.
Max.
10
Unit
mA mA mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
35 40 45 50
160 150 145 135 2
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 35 40 45 50
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
160 150 145 135 95 90 85 80 2.0
mA
ICC4
VCC Supply Current, EDO Page Mode Operation
35 40 45 50
mA
Minimum cycle
1, 2
ICC5 ICC6
VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby
mA
RAS = VIH, CAS = VIL other inputs VSS RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS CBR Cycle with tRAS tRASS (Min.) and CAS = VIL; WE = VCC-0.2V; A0-A8 and DIN = VCC-0.2V
1
2.0
mA
ICC7
Self Refresh Current
400
mA
VCC VIL VIH VOL VOH
Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
4.5 -1 2.4
5.0
5.5 0.8 VCC + 1 0.4
V V V V V IOL = 2 mA IOH = -2 mA 3 3
2.4
V53C808H Rev. 1.5 April 1998
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MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 35 #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V53C808H
40
45
50 Notes
Symbol
tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH tWP tWCR tRWL
Parameter
RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS (EDO) Access Time from RAS Access Time from Column Address CAS to Low-Z Output Output buffer turn-off delay time Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
35 70 25 35 7 16 0 0 6 0 4 14 5 0 23 75K 40 75 25 40 8 17 0 0 7 0 5 14 5 0 28 75K 45 80 25 45 9 18 0 0 8 0 6 15 5 0 32 75K 50 90 30 50 9 19 0 0 9 0 7 15 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4
5
15
0
0
0
0
ns
5
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
8 12 12 35 18 0 0 28 11 12 12 0 5 5 28 12 17 6
8 12 12 40 20 0 0 30 12 12 12 0 5 5 30 12 20 6
9 13 13 45 22 0 0 35 13 13 13 0 6 6 35 13 23 7
10 14 14 50 24 0 0 40 14 14 14 0 7 7 40 14 26 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12, 13 11 6, 7 6, 8, 9 6, 7, 10 16 16
V53C808H Rev. 1.5 April 1998
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MOSEL VITELIC
AC Characteristics (Cont'd)
35 #
32 33 34 35 36 37
V53C808H
40
45
50 Notes
14 14 14 14
Symbol
tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF tCOH
Parameter
Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in CAS Pulse Width (RMW) Col. Address to WE Delay EDO Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh EDO Page Mode Read-Modify-Write Cycle Time Transition Time (Rise and Fall) Refresh Interval (1024 Cycles) Output Hold After CAS Low
Min. Max. Min. Max. Min. Max. Min. Max. Unit
0 4 5 5 105 70 0 5 6 6 110 75 0 6 7 7 115 80 0 7 8 8 130 87 ns ns ns ns ns ns
38 39 40 41 42
28 54 46 35 14
30 58 48 38 15
32 62 50 41 17
34 68 52 42 19
ns ns ns ns ns
12 12
12
43 44 45 46 47
4 18 21 28 10
5 20 23 30 10
6 22 25 35 10
7 24 27 40 10
ns ns ns ns ns 7
48 49
0 8
0 8
0 10
0 12
ns ns
50
58
60
65
70
ns
51 52 53
3
50 16 5
3
50 16 5
3
50 16 5
3
50 16 5
ns ms ns
15
Optional Self Refresh
54 55 tRASS tRPS tCHS tCHD RAS Pulse Width During Self Refresh RAS Precharge Time During Self Refresh CAS Hold Time Width During Self Refresh CAS Low Time During Self Refresh 100 100 100 100 100 100 100 100 ms ns 18 18
56
100
100
100
100
ns ms
18
57
100
100
100
100
18
V53C808H Rev. 1.5 April 1998
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MOSEL VITELIC
Notes:
V53C808H
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VDD. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent). 17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. 18. Once CBR refresh or complete set of row refresh cycles must be completed upon exiting Self Refresh Mode.
V53C808H Rev. 1.5 April 1998
7
MOSEL VITELIC
Waveforms of Read Cycle
VIH VIL t CRP (13) CAS VIH VIL t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) t CAH (11) t RCD (6) t CSH (4) t RSH (R)(12) t CAS (5) t AR (23) t RAS (1) t RC (2) t RP (3)
V53C808H
RAS
t CRP (13)
COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15)
t RCS (7) WE VIH VIL
t ROH (16) t CAA (20) t HZ (22) t OAC (17) t CAC (18) t HZ (22) VALID DATA-OUT t LZ (21)
808H-05
OE
VIH VIL t RAC (19)
t HZ (22)
I/O
VOH VOL
Waveforms of Early Write Cycle
t AR (23) t RAS (1) t RC (2) t RP (3)
RAS
V IH V IL t CRP (13)
t RCD (6)
t CSH (4)
CAS
V IH V IL t RAH (9)
t RSH (W)(25) t CAS (5)
t CRP (13)
t ASR (8) ADDRESS V IH V IL ROW ADDRESS
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS t WCH (28)
t RAD (24)
WE
V IH V IL
t WP (29) t WCS (27)
t CWL (26)
t WCR (30) V IH V IL t DS (32) I/O V IH V IL t DHR (46)
t RWL (31)
OE
t DH (33) HIGH-Z
808H-06
VALID DATA-IN
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
8
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RAS (1) t RC (2) t RP (3)
V53C808H
RAS
V IH V IL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS
V IH V IL t RAD (24) t RAH (9)
t RSH (W)(12) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
t ASR (8) ADDRESS V IH V IL
ROW ADDRESS
COLUMN ADDRESS t CWL (26) t RWL (31)
t WP (29) WE V IH V IL
t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN
808H-07
I/O
Waveforms of Read-Modify-Write Cycle
tRRW (37) t RWC (36) t RP (3)
RAS
VIH VIL t CRP (13)
t AR (23)
t RCD (6)
t CSH (4)
CAS
VIH VIL t RAH (9) t ASR (8) VIH VIL ROW ADDRESS t RAD (24) VIH VIL t CAA (20) t OAC (17) t t ASC (10) COLUMN ADDRESS
t RSH (W)(25) t CRW (40)
t CRP (13)
CAH (11)
ADDRESS
t RCS (17) WE
t RWD (39)
t AWD (41) t CWD (38)
t RWL (31)
t CWL (26)
t WP (29)
OE
VIH VIL t OED (35) t CAC (18) t RAC (19) t HZ (22) VALID DATA-OUT t LZ (21) t DS (32) VALID DATA-IN
808H-08
t DH (33)
I/O
VIH VOH VIL VOL
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
9
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
V IH V IL t AR (23) t RCD (6) t CRP (13) CAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) V OH V OL t CAC (18) t COH VALID DATA OUT VALID DATA OUT t LZ t CAC (18) t CAR (44) t CAH (11) COLUMN ADDRESS t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t CRP (13) t CAS (5) t RAS (1) t
V53C808H
RP (3)
RAS
t CAS (5)
t ASR (8) ADDRESS V IH V IL V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
COLUMN ADDRESS
t RCH (14)
WE
t CAP (45)
t CAA (20) t OAC (17)
t RRH (15)
t HZ (22) VALID DATA OUT
t HZ (22) t HZ (22) t HZ (22)
I/O
808H-09
Waveforms of EDO Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) CAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL OE VIH V IL t DS (32) I/O V IH V IL
VALID DATA IN ROW ADD COLUMN ADDRESS
t RP (3) t RAS (1) t PC (42) t CP (43) t CAS (5) t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
t DH (33)
t DS (32)
t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
OPEN
OPEN
808H-10
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
10
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Write Cycle
RAS VIH V
IL
V53C808H
t RAS (1)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V CAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RWD (39) t RCS (7) V WE V
IH IL
t CWD (38)
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t CAA (20)
t CAP (43)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN
808H-11
IN
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
t RC (2) V IH V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADD
808H-12
t RAS (1)
t RP (3)
RAS
t RAH (9)
WE, OE = Don't care
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
11
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS V IH V IL t CSR (47) CAS V IH V IL V IH V IL READ CYCLE V IH V IL t ROH (16) t OAC (17) OE V IH V IL t LZ (21) I/O V IH V IL WRITE CYCLE t WCS (27) WE V IH V IL V IH V IL t DS (32) I/O V IH V IL t DH (33) D IN t RWL (31) t CWL (26) t WCH (28) DOUT t CHR (49) t CP (43) t RSH (W)(25) t CAS (5)
V53C808H
t RP (3)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
WE
t HZ (22) t HZ (22)
t HZ (22)
OE
808H-13
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A 0 -A 9 = Don't care
808H-14
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
12
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O V OH V OL VALID DATA t HZ (22) t HZ (22) t OAC (17) t HZ (22)
ROW ADD
V53C808H
t RAS (1) t AR (23)
tRP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t RCS (7) WE
t RRH (15)
OE
808H-15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL V IH OE V IL t DS (32) I/O V IH V IL t DH (33)
VALID DATA-IN ROW ADD
t RAS (1) t AR (23)
t RP (3)
t RC (2) t RAS (1)
t RP (3)
RAS
t RSH (12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t WCS (27) WE
t WCH (28)
t DHR (46)
808H-16
Don't Care
V53C808H Rev. 1.5 April 1998
Undefined
13
MOSEL VITELIC
Waveforms of Self Refresh Cycle (Optional)
tRP (3) RAS VIH VIL tRPC (48) tRPC (48) tCP (43) UCAS, LCAS VIH VIL VIH VIL tCSR (47) tCHD (57) tCHS (56) tRASS (54) tRPS (57)
V53C808H
ADDRESS
I/O
VOH VOL
OPEN
WE
VIH VIL
OE
VIH VIL
808H-17
Functional Description
The V53C808H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C808H reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
V53C808H Rev. 1.5 April 1998
14
MOSEL VITELIC
Extended Data Output Page Mode
EDO Page operation permits all 1024 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 72 MHz for applications that require high bandwidth such as bitmapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 1024 Data Rate = ------------------------------------------t RC + 1023 t PC
V53C808H
Self Refresh (Optional)
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of inactivity. Device operation in this mode provides additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initialed with a CAS before RAS (CBR) Refresh cycle, holding both RAS low (tRASS) and CAS low (tCHD) for a specified period. Both of these parameters are specified with minimum values to guarantee entry into Self Refresh operation. Once the device has been placed in to Self Refresh mode the CAS clock is no longer required to maintain Self Refresh operation. The Self Refresh mode is terminated by returning the RAS clock to a high level for a specified (tRPS) minimum time. After termination of the Self Refresh cycle normal accesses to the device may be initiated immediately, poviding that subsequest refresh cycles utilize the CAS before RAS (CBR) mode of operation.
Data Output Operation
The V53C808H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
V53C808H Rev. 1.5 April 1998
15
MOSEL VITELIC
Power-On
After application of the VCC supply, an initial pause of 200 ms is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C808H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
V53C808H
Table 1. V53C808H Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
V53C808H Rev. 1.5 April 1998
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MOSEL VITELIC
Package Diagrams
28-Pin Plastic SOJ
V53C808H
Unit in inches [mm] 0.725 0.005 [18.42 0.12] 28 15
0.400 0.005 [10.16 .0.13]
0.440 0.005 [11.18 0.12]
1
14
+0.007 0.138 -0.006 0.028 +0.102 +0.004 0.711 -0.051 -0.002 3.51 +0.178 -0.154
0.043 MAX [1.09 MAX] 0.004 [0.102] 0.05 bsc [1.27 bsc] 0.015/0.020 [0.38/0.51] 0.025 MIN [.635 MIN]
V53C808H Rev. 1.5 April 1998
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0.370 0.010 [9.40 0.26]
MOSEL VITELIC
U.S.A.
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WORLDWIDE OFFICES
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V53C808H
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U.S. SALES OFFICES
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3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
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(c) Copyright 1997, MOSEL VITELIC Inc.
4/98 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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